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STU2071
4B3T U INTERFACE CIRCUIT
PRELIMINARY DATA
4B3T TWO-WIRE U INTERFACE CIRCUIT FOR LT AND NT APPLICATION 120 kbaud LINE SYMBOL RATE (120 SYMBOLS PER FRAME) SCRAMBLER AND DESCRAMBLER ACCORDING TO CCITT REC V.29 BARKER CODE (11 SYMBOLS) SYNCHRONIZATION WORD UNSCRAMBLED 1 KBIT/S HOUSEKEEPING CHANNEL ADAPTIVE ECHO CANCELLATION WITH TRANSVERSAL FILTERING ADAPTIVE DECISION FEEDBACK EQUALIZATION AUTOMATIC GAIN CONTROL PDM AD CONVERTER AUTOMATIC ACTIVATION AND DEACTIVATION WITH POLARITY ADAPTION AUTOMATIC CODE VIOLATION DETECTION POWER FEED UNIT CONTROL ADVANCED CL3 1.5m CMOS PROCESS 28 PIN DUAL-IN-LINE PLASTIC PACKAGE V* DIGITAL INTERFACE
DIP28 ORDERING NUMBER: STU2071B1
PLCC28 ORDERING NUMBER: STU2071FN
SYSTEM OVERVIEW STU2071 (UIC) provides two transparent 64 kbit/s B channels, a transparent 16 kbit/s D channel, a transparent 1 kbit/s service channel and a 1 kbit/s maintenance channel for loop and error messages on subscriber lines. UIC enables full duplex continuous data transmission via the standard twisted pair telephone cable. Adaptive Echo cancellation is used to restore the received data. An equalizer, done with an adaptive filter, restores the data which are distorted by the transmission line. The coefficient of the equalizer and echo canceller are conserved during a power down. An all digital PLL performs both bit and frame synchronization. The analog front end consists of receive path RX and transmit path TX, providing a full duplex analog interfacing to the twisted pair telephone cable. Before data are converted to analog signals, they
September 1994
pass through a digital filter (TX-filter) to reduce the high frequency components. After D/A conversion the signal is amplified and sent to the hybrid. The received signal is converted back to digital data and passed through the RX matching filter to restore the line signal. The A/D convertor is a second order sigma/delta modulator which operates with a clock of 15.36 MHz. After timing recovery, achieved by a digital PLL, the received signal is equalized, in an adaptive digital filter, to correct for the frequency and group delay distortion of the line. Power supply status can be read via PFOFF. The UIC can disable its power supply (DISS), and two relay drivers outputs are provided (accessible via B2*) to control the power feed unit (RD1,RD2).
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STU2071
PIN CONNECTION (Top view)
PFOFF
XTAL2
27
4 DISS/COEF RESETN 5 6 7 8 9 10 11 12
3
2
1
28
26 25 24 23 LIN2 LIN1 LOUT2 AGND AVDD LOUT1 AVSS
DIP28
DIN TSP BURST FR DOUT
PLCC28
XTAL1
22 21 20 19 18
DVSS
15
TEST
13
14
16
CLS S1
LT
17
S2
S0
DVDD
CL
RD1
RD2
D93TL041
Figure 1: UIC Schematic Block Diagram
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STU2071
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16, 17 18 19 20 21 22 23 24,25 26, 27 28 Name DVSS(input) PFOFF(input) LT(input) TEST(input) DISS(output) RESETN(input) DIN(input) TSP(input) BURST(input) FR(in/out) DOUT(output) CL(in/out) RD1(output) RD2(output) S2,S1,S0 DVDD(input) AVSS(input) LOUT1(output) AVDD(input) AGND(input) LOUT2(output) LIN1,LIN2(input) XTAL1,XTAL2(inputs) CLS(output) Digital Ground. Power feed off. PFOFF=HIGH is coded by the A-bit indication HI accessible on DOUT. Active in LT mode only. LT/NT mode selection. Test Mode. A bit channel driven pin. Active in LT mode only. Hardware Reset. Digital interface input. Transmit single pulse. 1 KHz single pulse alternating positive and negative polarity is transmitted. Burst mode selection. Active in LT mode only. 8KHz Digital interface frame clock; input in LT and output in NT mode. Digital interface output. Digital interface bit clock; input in LT and output in NT mode. Power feeder relay driver. Power feeder relay driver. Time slot pin strap (. Active in LT mode only. 5V +/-5% positive digital power supply. Analog Ground. Output to the line. 5V +/-5% positive analog power supply. Analog Ground. Output to the line. Inputs from the line (UK0). System clock input;nominal frequency is 15.36MHz. Clock output synchronous to the line receive clock at 7.68MHz. Function
In LT burst:
APPLICATION AND MODES The UIC can be used in LT, LT-burst and in NT mode. Hereafter a list of the pin bias to set up the desired mode is given.
In LT mode:
Pins LT BURST S0 S1 S2
In NT:
Value 1 1 time slot time slot time slot Value 0 0 0 0 1
Pins LT BURST S0 S1 S2
Value 1 0 0 0 0
Pins LT BURST S0 S1 S2
Test pins should always be tied to GND
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STU2071
MODE DEPENDENT FUNCTIONS PIN
LT BURST S2, S1, S0 DIN DOUT CLS (MHz) CL (KHz) FR (KHz) input input input input output output input output input output
LT burst 1 1 static 2048 kbit/s 7.68 4096 - 8 -
NT 0 0 100 256 kbit/s 7.68 - 512 - 8
MODE LT 1 0 000 256 kbit/s 7.68 512 - 8 -
LTRP 0 0 001 256 kbit/s - 512 - 8 -
NTRP 0 0 010 256 kbit/s 7.68 - 512 - 8
RECOMMENDED APPLICATIONS LT mode Figure 2: LT Schematic Application Diagram
DIN: DOUT: CL: FR: XTAL2: CLS:
Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz
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STU2071
NT mode Figure 3: LT Schematic Application Diagram
DIN: DOUT: CL: FR: XTAL1/2: CLS:
Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1) 15.36 MHz Xtal connection (Clock not synchronous to system clock) Clock output, 7.68 MHz (used to synch S interface)
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STU2071
LT burst mode Figure 4: LT Burst Mode Schematic Application Diagram.
DIN: DOUT: CL: FR: XTAL2: CLS:
Data input, datarate = 2048 kbit/s, continuous Data output, datarate = 2048 kbit/s, continuous Data clock input, f = 4096 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz
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STU2071
Figure 5: Repeater Block Diagram.
To line - NT side A-wire
To line - LT side A-wire
UIC LTrep
DOUT DIN
DIN DOUT CL FR
UIC NTrep
HYBRID
CL FR
HYBRID
XTAL2 XTAL2 B-wire CLOUT 512KHz CLOUT 512KHz 15.36MHz PHASE COMPARATOR AND LOOP FILTER(*) XTAL1 5V 0V B-wire
15.36MHz
VCO 15.36MHz
DC/DC
PLL circuit
50mH 2.2F 50mH
D94TL099
2.2F
(*)1st order loop filter is sufficient (3dB frequency at 100Hz approx.)
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STU2071
DIGITAL INTERFACE UIC is provided with a digital serial interface, named V*, which operates in two modes. In Fig. 6 the frame format for both modes is shown. The base frame consists of: B1 : 64 kbit/s transparent data channel B2 : 64 kbit/s transparent data channel B2* : Monitor channel B1* : 8 bits so set D1/D2 : 16 kbit/s D channel A1..A4 : Command/Indicate channel T : Transparent service channel E : Extension bit In Fig. 7 and 8 the timings in Continuous and in Figure 6: V* Frame Format. Burst mode are given. B2* available messages (do not use in REPETER modes):
Code 74H 75H 76H 77H EFH (F0-FF)H All others Function Set RD1 to HIGH Set RD2 to HIGH Set RD1 and RD2 to HIGH Reset RD1 and RD2 to LOW Reset frame error counter NOD Not defined
In Fig. 7 and 8 the timings in Continuous and in Burst mode are given.
Figure 7: Continuous Mode.
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STU2071
Figure 8: Burst Mode.
LINE FRAME STRUCTURE. The information flow across the subscriber line
1 T1 T1 T1 T2 T2 T3 T3 T4 T4 T4 1 T5 T5 M2 T6 T6 T6 T7 T7 T8 T8 2 T5 T5 T5 T6 T6 T7 T7 T8 T8 3 T5 T5 T5 T6 T6 T7 T7 T8 T8 4 T5 T5 T5 T6 T6 T7 T7 T8 T8 5 T5 T5 T6 T6 T6 T7 T7 T8 T8 6 T5 T5 T6 T6 T6 T7 T7 T8 T8 2 T1 T1 T1 T2 T2 T3 T3 T4 T4 3 T1 T1 T1 T2 T2 T3 T3 T4 T4 4 T1 T1 T2 T2 T2 T3 T3 T4 T4 5 T1 T1 T2 T2 T2 T3 T3 T4 T4 6 T1 T1 T2 T2 T2 T3 T3 T4 T4 7 T1 T1 T2 T2 T3 T3 T3 T4 T4 SW1 7 T5 T5 T6 T6 SW2 T7 T7 T7 T8 T8 8 T5 T5 T6 T6 T7 T7 T7 T8 T8 8 T1 T1 T2 T2 T3 T3 T3 T4 T4
uses the frame structure here below. The length of one frame corresponds to 120 ternary symbols being transmitted within 1 ms.
9 T1 T1 T2 T2 T3 T3 T3 T4 T4 10 T1 T1 T2 T2 T3 T3 T4 T4 T4 11 T1 T1 T2 T2 T3 T3 T4 T4 T4 12 T1 T1 T2 T2 T3 T3 T4 T4 T4 24 36 48 60 72 84 96 108 120 9 T5 T5 T6 T6 T7 T7 T7 T8 T8 19 T5 T5 T6 T6 T7 T7 T8 T8 T8 11 T5 T5 T6 T6 T7 T7 T8 T8 T8 12 T5 T5 T6 T6 T7 T7 T8 T8 T8 24 36 48 60 72 84 96 108 120 NT LT LT NT
Agenda: T1. . . . . .T8 M1, M2 SW1, SW2
B + B + D - Data (ternary) Service Data (ternary) Synchronizing Word
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STU2071
Maintenance and service channel. The ternary symbols M1 and M2 represent nonscrambled data that can be transmitted at a rate of 1 kBaud. Those symbols are used for various purposes: - Maintenance Channel (control test loops (LT NT) and frame errors (LT NT) - Service channel (transparent user data and transmit messages from NT to LT) Encoding. The encoding of a binary bit stream is made such that 4 binary bits correspond to 3 symbols of ternary symbol stream. The encoding follows the rules of modified monitoring state 43 (MMS43).
COMMAND / INDICATE CHANNEL (A bits) Command/Indicate codes are define depending on the mode selected (LT or NT). NT mode COMMANDS (DIN)
ACT 1000 Activate. Layer 1 is activated at the UK0 interface starting with a 'wake-up' signal INFO U1W, followed by INFO U1A during synchronization and closed by INFO U1 when synch is gained. Awake. Set the module interface from the power-down to the power-up state. No signal is emitted at UK0 interface. Even DIN pin pulled LOW can have the same effect. Deactivation confirmation. The module interface is deactivated. The transmitter is disabled but the receiver is still enabled to recognize an awake signal. THe UIC is set in power down state. Reset. Reset the UIC to the initial state. Synchronize. Drive the UIC in connect through from module interface to line interface.
AW
0000
DC
1111
RES SY
1101 1100
Remark: Executing the command RES (1101) is functionally equivalent to pulling the RESETN pin (6) LOW, with one exception: a) RES command set pin DISS to HIGH (+5V) b) pulling RESETN LOW set pin DISS to LOW (0V). NT mode INDICATION (DOUT)
ACT DC 1000 1111 Activate. The synchronous state of the receiver is reached. Deactivation confirmation. The transmitter is disabled but the receiver remains enabled to detect awake signals at UK0 UIC is set in power down state. Deactivate. A request to deactivate INFO U0 has been detected. Connection Through. The UIC is fully activated. Connection through with loop 2. A loop 2 command has been detected at UK0. Loop 2. Synchronization has been reached during a Loop 2 activation procedure. Resynchronization. The receiver has lost framing and is attempting to resynchronize.
DEAC CT CTL2 L2 RSYN
0000 1100 1110 1010 0100
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STU2071
LT mode COMMANDS (DIN)
ACT 1000 Activate. UIC is set in power-up state, executing the complete activation of Layer 1. The transparent channel transmission is enabled. Analog Loop. The analog transmitter output is looped back to the receiver input which is disconnected from UK0 interface. A pseudo wake-up procedure is executed. Loop 2. Command to close Loop 2 in NT. Line Transmission Disabled. UIC stops transmitting signals on the line and is powered down. Deactivate. Request to deactivate UK0. Reset. Reset the UIC to the initial state. Send Single Pulse. The UIC transmits single pulse at 1 ms time intervals with alternate polarity. Repeter loop
AL
1001
L2 LTD DEAC RES SSP L4
1010 0011 0000 1101 0101 1011
LT mode INDICATION (DOUT)
ACT RDS CT 1000 0111 1100 Activation running. UIC is powered-up and the activation procedure is running. Running Digital Sum. Given during activation procedure. The receiver has reached synchronization. Connection Through. Layer 1 activation procedure has been completed. B and D channels are transparently connected. Deactivation running. UIC is deactivating in response of a DEAC, RES or LTD command. Deactivation confirmation. UIC has completed the deactivation procedure. Resynchronization. The receiver has lost framing and is attempting to resynchronize. High Impedance. When pin PFOFF is HIGH indication HI is output and UIC starts transmitting INFO U0. Normally used to indicate that remote feeding has been switched off.
DEAC DC RSYN HI
0001 1111 0100 0011
POWER DOWN STATE Power consumption of most functions is reduced; module interface is not active; C/I messages cannot be exchanged. ACTIVATION DEACTIVATION The ACTIVATION procedure consists of three steps: AWAKE, SYNCHRONIZE and CONNECT THROUGH. Activation times are (max): COLDSTART 1 sec WARMSTART 170 msec The DEACTIVATION procedure consists of two steps: line DEACTIVATION and POWER DOWN. Deactivation time is (typ) 4 ms.
OSCILLATOR Oscillators of 15.36 MHz are required. When in NT a tollerances of +/-30 ppm is allowed, it is advisable to use in LT a tollerances of +/-20 ppm. LINE RANGE The LINE RANGE depends on the cable section. Typically: up to 4.2Km with 0.4mm cable - 5.5Km - 0.5mm - 8.0Km - 0.6mm Assumed noise level for such performances is 10uV/SQRT(Hz) on a 200KHz bandwidth. LT CLOCK JITTER The phase jitter between Master Clock (15.36MHz) and interface clock (4.096MHz) should not exceed 50ns.
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STU2071
ELECTRICAL CHARACTERISTICS Supply Voltages: DVDD = 5V +/- 5% AVDD = 5V +/- 5% AGND = 2.5V +/- 5% (max curr 0.25mA) Power consumption Active = max 280mW (line loaded at 150Ohm) Power down = Typ. 30mW = Max. 50mW DIGITAL INTERFACE STATIC CHARACTERISTICS
Symbol VIH VIL VOH1 VOH2 VOL1 VOL2 CIN COUT COUT IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage all outputs except DOUT High Level Output Voltage DOUT, (Open Drain) Low Level Output Voltage all outputs except DOUT Low Level Output Voltage DOUT, (Open Drain) Inputs Capacitance, all inputs at DOUT if output is off Load Capacitance at all outputs except at DOUT Load Capacitance at DOUT Input Leakage Current IOH1 = 0.4mA R to DVDD R = 1K IOL1 = 0.4mA IOL1 = 0.7mA VDD0.66 4 0.33 0.4 10 10 25 150 1 Test Condition Min. 3.5 1.0 Typ. Max. Unit V V V V V V pF pF pF pF A
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STU2071
DIGITAL INTERFACE DYNAMIC CHARACTERISTICS Burst mode.
Conditions Parameter Rise Time tr Fall Time tf Setup Time ts Setup Time ts Setup Time ts Setup Time ts Hold Time th Hold Time th Hold Time th Hold Time th Delay Time td Delay Time td Clock Width tc Clock Width tc Port FR, CL FR, CL FR FR DIN MPF FR FR DIN MPF DOUT DOUT CL, i CL, i from 1.0V 3.5V FR, i - FR, i + DIN +/- MPF +/- CL, i + CL, i + CL, i + CL, i + CL, i - CL, i - CL +/- CL +/- to 3.5V 1.0V CL, i + CL, i + CL, i + CL, i + FR, i - FR, i + DIN +/- MPF +/- DOUT +/- DOUT +/- CL +/- CL -/+ 50 150 1 1 C pF 10 10 30 30 50 50 50 50 60 60 0 0 239 100 150 200 249 144 R to DVDD K Min. ns Max. ns 30 30
+ = rising edge - = falling edge
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STU2071
DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Continuous mode.
Conditions Parameter Rise Time tr Fall Time tf Rise Time tr Fall Time tf Setup Time ts Setup Time ts Delay Time td Hold Time th Hold Time th Delay Time td Setup Time ts Setup Time th Delay Time td Delay Time td Clock Width tc Clock Width tp Pulse Width tp Pulse Width tp Port FR, CL, i FR, CL, i FR, CL, o FR, CL, o DIN MPF FR DIN MPF DOUT DIN DIN DOUT FR CL, i CL, i CL, i CL, i from 1.0V 3.5V 10% 90% DIN +/- MPF +/- CL, i + CL, i - CL, i - CL, i + DIN +/-1 CL, o - CL. o + CL, o + CL +/- CL +/- CL +/- CL +/- to 3.5V 1.0V 90% 10% CL, i + CL, i + FR, i + DIN +/- DIN +/- DOUT +/- CL, o + DIN +/- DOUT +/- FR,o + CL +/- CL +/- CL -/+ CL -/+ C pF 10 10 25 25 50 50 -200 100 100 25 10 50 100 25 25 25 25 10 -150 1830 1830 850 850 500 150 2080 2080 1100 1100 R to DVDD K Min. ns Max. ns 30 30 30 30
200 500
+ = rising edge - = falling edge
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STU2071
DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Master clock.
Conditions Parameter Rise Time tr Fall Time tf Rise Time tr Fall Time tf Pulse Width Port XTAL2 XTAL2 CLS CLS CLS from 1.0V 3.5V 10% 90% CLS +/- to 3.5V 1.0V 90% 10% CLS -/+ C pF 10 10 25 25 25 20 Min. ns Max. ns 15 15 15 15
+ = rising edge - = falling edge
Setup Time ts Hold Time th Delay min. td Delay max. td Delay min. td (negative) Delay max. td Setup Time ts Hold Time ts Delay max. td Delay min. td (negative) Delay max. td Pulse Width tp Clock Width tc Pulse Width tp Clock Width tc
DIN, FR, i +/- CL, i + CL, i + CL, i - CL, i + CL, i - CL, i + CL, i + DIN, +/- CL, o + CL, o + CL, o + CL, o + CL, o +/- CL, o +/- CLS, MXCL +/- CLS, MXCL +/-
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
CL, i + DIN, FR, i +/- DOUT +/- DOUT +/- FR, i + FR, i + CL, o + DIN +/- DOUT +/- FR, o + FR, o + CL, o -/+ CL, o +/- CL, o -/+ CL, o +/-
2.5V 2.5V 0.4 / 4V 4 / 0.4V 3.5V 1V 2.5V 2.5V 4 / 0.4V 0.33V VDD - 0.66V 2.5V 2.5V 2.5V 2.5V
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STU2071
DIP28 PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.130 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
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STU2071
PLCC28 PACKAGE MECHANICAL DATA
DIM. MIN. A B D D1 D2 E e e3 F F1 G M M1 1.24 1.143 12.32 11.43 4.2 2.29 0.51 9.91 1.27 7.62 0.46 0.71 0.101 0.049 0.045 10.92 mm TYP. MAX. 12.57 11.58 4.57 3.04 MIN. 0.485 0.450 0.165 0.090 0.020 0.390 0.050 0.300 0.018 0.028 0.004 0.430 inch TYP. MAX. 0.495 0.456 0.180 0.120
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STU2071
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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